Scientific Computation on PlayStation 2:
Emotion Engine CPU
The potential of the PlayStation 2 for scientific use stems from the two
specialized vector processing units that are part of the Emotion Engine CPU. The
layout of the Emotion Engine is shown here:
Figure is Copyright Sony Computer Entertainment Inc. Used
with permission. This figure may not be copied or re-distributed without written
permission of the Copyright holder.
The Emotion Engine has the
following external connections: the video sync sub-system drives the CPU clock.
The EE connects to 32 MB of RDRAM through the DRAM Controller. Connections to
the disk drive, ethernet and USB are handled by the IO Processor, via the
Sub-processor InterFace (SIF). Finally, the EE connects to the Graphics
Synthesizer via the Graphics InterFace unit (GIF).
Core
The CPU core is a mips R3000 compatible general purpose processor. It has the
same relationship with the rest of the PlayStation 2 as the CPU has in a
conventional computer (Pentium or Power-PC, for example). The core runs the
Linux kernel, the operating system, and any programs that are compiled
conventionally.
The core has a full mips-3 instruction set, with extensions from mips-4 and
mips-5. The core also has 128-bit multi-media instructions specific to the
Emotion Engine design. The mips compliance makes it easy to port existing code
that already runs under mips Linux.
Vector Units
The Emotion Engine also contains two Vector Processing Units, VU0 and VU1.
These are calculation engines that perform vector and matrix operations with
high throughput (four floating-point multiply-adds per clock). The VUs have a
their own instruction and data memories, and have a different instruction set
than the CPU core. An overview of the VU's components:
Figure is Copyright Sony Computer Entertainment Inc. Used with
permission. This figure may not be copied or re-distributed without written
permission of the Copyright holder.
Data Format
The vector unit uses 4-component vectors (containing X, Y, Z, and W fields)
as operands. Each field is a 32-bit (single-precision) floating point number,
thus all the main data pathways inside the Emotion Engine are 128 bits wide.
The Emotion Engine stores 32-bit floating point numbers equivalently to IEEE
754 single precision (8 bit exponent, 23 bit mantissa), but does not fully
implement that standard. The vector units do not explicitly support NANs, INFs,
or non-normalized values. They also do not halt if a floating point exception
occurs (dividing by zero for instance). Instead, a bit in a status register is
set, which must be checked by user code. The Emotion Engine does not support
64-bit floating point values.
Execution Units
The vector unit has two execution units, "upper" and "lower". Machine
instructions (for micro-mode execution) are 64 bits, with one half controlling
each of the execution units. The two units execute in parallel, one instruction
per clock. The upper execution unit controls the FMACs, and so upper
instructions are multiply and/or add instructions. The lower execution unit
controls the divider, and also does integer operations, loads, stores, jumps,
and general register operations.
The upper execution unit contains four Floating-point Multiply-Accumulators.
Each FMAC can execute a multiply-add sequence every clock tick. This means that
each VU can calculate a matrix times vector (4x4 times 4x1) in 7 clocks
(throughput of 4), and a 4x4 matrix times matrix calculation in 19 clocks
(throughput of 16).
The lower execution unit contains the other functional units. These include
the division unit that calculates reciprocals and square roots. Also included
are a random number generator, load-store unit, integer operation unit, and a
branch unit. VU1 additionally contains a elementary function unit, for
evaluating trigonometric functions.
Macro and Micro Mode
The vector unit design has two operational modes. In "macro" mode, the VU
acts as a co-processor to the MIPS core, executing co-processor calls. Only VU0
operations in this fashion. The other mode is "micro" mode, where the VU fetches
instructions from its own instruction ("micro") memory and executes them. Both
VU0 and VU1 can be used in this mode.
Memory in the Vector Unit
Each Vector Unit has an instruction memory, or "Micro Memory", from which it
fetches programs. It also has a working data memory, or "VU Memory", that
contains input and output data. The Vector Units cannot access main RAM, they
must have their data placed in their respective VU Memories before processing
can start. One of the challenges of using the VU successfully is to move
information in and out of the VU Memories quickly. VU0 has 4KB of both types of
memory, VU1 has 16KB.
VU0/VU1 comparison
Summary of the important similarities and differences between the Vector
Units:
|
VU0 |
VU1 |
| Macro Mode |
yes |
no |
| Micro Mode |
yes |
yes |
| Micro Mem size |
4 KB |
16 KB |
| VU Mem size |
4 KB |
16 KB |
| EFU |
no |
yes |
|
|
|
VIFs and DMAC
The Micro Memory and VU Memory of the VUs are accessible to the core via
memory accesses, but only while the VU is stopped (or in Macro Mode). The VIFs
(Vector InterFace unit) provid pathways for data into the VUs while the VUs are
executing code. This is vital to using the VUs efficiently.
The VIF does not fetch instructions; instead, packets of VIF instructions
along with VIF data are packed into memory and transferred to the VIF using the
DMA controller. 2 of the DMA channels are dedicated to VIF communication.
According to instructions included in the packet, the VIF can load programs into
the micro-memory, load data into the VU memory, execute micro-programs, or pause
for synchronization. VIF instructions via DMA is the primary method for
controlling the execution of the VUs.
The DMAC (DMA Controller) controls memory access between RAM and other
periphrials (any non-Core device; SPR, VU1, VU2, GIF, etc.). A very important
feature of the DMAC is its "source chain" transfer mode. In this mode the DMA
controller takes the first quadword (128 bit block) in its source in RAM and
interprets that quadword as an instruction as to what to transfer next. That
includes transferring data from another part of memory to the target and then
returning to the following location for its next instruction (called a
"reference" DMA tag).
The practical upshot of the arrangement of the VIFs and the DMAC is that the
programmer can assemble a list of information to be transferred to the VU Memory
through the VIF. Using the DMA reference tags, as mentioned above, data can be
transferred without having to be assembled into a specific area in memory. Thus
the programmer can move a piece of existing data in RAM without having to
manipulate it first. This capability is used to transfer a small portion of a
parameter matrix to the VU to be used as part of a multiplication.
For additional information or questions about the project, please contact Craig Steffen
Scientific Computation on
PlayStation 2 home page